Wednesday, February 12, 2025
ElectronicsBOS and Tenstorrent Unveil Eagle-N, Industry's First Automotive AI Accelerator Chiplet SoC

BOS and Tenstorrent Unveil Eagle-N, Industry’s First Automotive AI Accelerator Chiplet SoC

BOS Semiconductors, the Korean automotive fabless company, and Tenstorrent, an AI design company, announced the first debut of industry’s first automotive AI accelerator chiplet SoC, Eagle-N, jointly developed by BOS and Tenstorrent. The Eagle-N incorporates Tenstorrent’s Tensix NPU core, which is tailored for automotive applications and delivers the powerful AI performance and energy-efficient operation for Automotive Advanced Driver Assistance Systems (ADAS) and In-vehicle infotainment (IVI) domain computing system.

BOS Eagle SoC, the industry’s first automotive chiplet AI accelerator

Eagle-N provides up to 250TOPS NPU performance along with PCIe gen5 and UCIe high-speed interfaces to build an add-on NPU and AI subsystem to develop autonomous driving functions and immersive in-cabin experiences leveraging chiplet technology. Every kind of ADAS and IVI processor in the market can be connected with Eagle-N and OEMs/Tier-1s can simply implement Eagle-N on top of their existing ADAS or IVI domain computing system to upgrade its AI performance while enjoying Eagle-N’s TOPS/$ and TOPS/watt competitiveness.

In addition to Eagle-N, BOS is also committed to developing Eagle-A, which is an one-chip ADAS SoC and can be used in conjunction with Eagle-N. Eagle-N and Eagle-A are ADAS chiplet SoC family to support various segments of ADAS and autonomous driving functions.

“It is very exciting to introduce our first automotive SoC product to the market.” said Jaehong Park, CEO and founder of BOS Semiconductors. “Eagle-N is the first series of our Eagle ADAS Chiplet SoC family. Along with Tenstorrent, we will provide the most cost-effective, high-performance and low-power AI SoC in the automotive industry.”

Tenstorrent Tensix NPU cores and its chiplet eco-system

Each of Tenstorrent’s Tensix Core includes an array math unit for tensor operations, a SIMD unit for vector operations, a Network-on-Chip (NoC) to move data from core-to-core and chip-to-chip, five “baby RISC-V” processors to help direct the NoC, and up to 1.5MB of SRAM.

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